Semiconductor Project Execution
Semiconductor project execution is governed by a dependency chain that is non-negotiable: verification must complete before tapeout, tapeout must complete before silicon arrives, and silicon must arrive before post-silicon validation can begin. The cost of a missed foundry window is measured in months and non-recurring engineering budgets. The cost of a post-silicon surprise that requires a re-spin is measured in quarters. Managing semiconductor programs requires a PM who understands where these dependencies live — not just the Gantt chart dates, but the technical states that must be true before each phase transition is valid.
Where Semiconductor Execution Breaks Down
Verification plans drafted retrospectively — after design is underway — produce testbenches that cover what was convenient to test rather than what must be demonstrated correct. The verification plan must exist before RTL development begins, with coverage targets derived from architectural assumptions.
Foundry communication managed through an individual engineer without formal program governance creates single points of failure for schedule-critical information: PDK updates, shuttle window changes, tape-in package requirements. Foundry coordination is a program management function, not a personal relationship.
Post-silicon validation plans that describe only bench characterization leave regulatory certification, production test coverage, and hardware-software integration as unscoped work to be defined after silicon arrives. These workstreams have long lead times and must be planned before tapeout.
Program schedules built from business commitments backwards — without input from design, verification, and physical design leads on what the engineering work actually requires — produce plans that have no relationship to the technical dependency chain. The schedule collapses at first contact with reality.
ASIC Delivery Lifecycle — Six Phases
System requirements specification, microarchitecture definition, IP sourcing and licensing, PDK and foundry selection, technology node qualification, and preliminary area/power/timing estimates. Architecture Decision Records written. Product definition baseline signed before design entry.
RTL coding, linting, functional simulation, assertion-based verification, and coverage closure. Verification plan drives simulation prioritization — not calendar proximity to next milestone. Block-level and chip-level coverage targets defined and tracked. Regression infrastructure operational throughout RTL phase.
Floorplanning, placement, routing, clock tree synthesis, timing analysis across all corners, power grid analysis, and signal integrity review. DFT insertion: scan chains, BIST, JTAG, memory BIST. Formal verification of RTL-to-netlist equivalence. Physical design sign-off checklist completed before tape-in package assembly.
DRC, LVS, ERC, antenna rule checks, density checks — all clean against the production PDK. Timing sign-off at all required corners including post-layout extracted parasitics. Tape-in package assembled: GDS-II, Verilog netlist, SPEF, LEF, timing models, test vectors. Tapeout readiness review completed before foundry submission.
Silicon bring-up against pre-written bring-up plan. Functional validation against specification with ATE or bench vectors. Hardware-software integration: firmware, drivers, and application layer validated against production silicon. Characterization across voltage, temperature, and frequency. Errata documented. Re-spin decision made with engineering data, not optimism.
ATE program handoff, production test coverage validation, yield analysis, reliability testing (HTOL, ESD, latch-up), regulatory certification (if applicable), and supply chain qualification. Production ramp plan with yield targets, test time targets, and volume ramp milestones.
Verification Dependency Chain
Every phase transition in a semiconductor program has a predecessor dependency that must be true before the transition is valid. Programs that ignore these dependencies produce schedules that fail at the first real milestone review. The following dependencies are structural — they cannot be reordered without creating downstream risk.
Coverage model and testbench architecture defined before RTL begins. Testbench developed in parallel with RTL, not after.
Regression infrastructure (CI/CD, compute allocation, coverage database) operational before coverage-driven simulation begins.
PDK version frozen before floorplan begins. Version drift after physical design entry is a re-start, not an incremental update.
SDC complete and reviewed before synthesis is run. Post-synthesis constraint creation is reactive and produces unreliable results.
ATE program, bring-up fixtures, firmware baseline, and characterization test plan in place before silicon is submitted. Silicon arrives into a prepared validation environment, not an empty lab.
Certification activities (UL, FCC, CE, MIL-SPEC) planned before tapeout because lead times frequently exceed silicon turnaround time.
Foundry Coordination Governance
Foundry shuttle calendar maintained with tape-in deadlines, wafer delivery dates, and MPW partner coordination. Window slips tracked as program risks with business impact quantified.
PDK version frozen at physical design entry. PDK updates after lock assessed as change requests with full impact analysis on physical design, timing, and verification — not accepted silently.
Tape-in package checklist: GDS-II, Verilog netlist, SPEF, timing models, test vectors, DRC/LVS reports, design rule waivers, reuse agreements. PM owns the checklist; engineering owns the content.
Escalation path for foundry issues defined in advance: technical queries, yield excursions, schedule changes, and DRC rule clarifications each have a defined owner and response SLA on both sides.
Related Services and Resources
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